1. Field of the Invention
The present invention relates to microprocessors that execute context switching, particularly to microprocessors that have a plurality of sets of context information.
2. Description of the Related Art
Microprocessors that carry out multitask processing to execute plural programs in parallel are well known. Program execution in multitask processing by such microprocessors is suspended by an external interrupt or the like. Generally, when program execution is suspended, a microprocessor stores information (hereafter, referred to as ‘context information’) that indicates previous execution status of the suspended program and the microprocessor's status in a memory unit.
When a suspended program is resumed, a microprocessor is restored to the status before suspension by reading the context information stored in the memory unit. Storing execution statuses of multiple programs in the memory unit as context information respectively, and changing the context information to be used by a microprocessor for multitask processing is referred to as ‘context switching’.
There is a method for a microprocessor to store a plurality of sets of context information using a register bank architecture or a register window architecture. However, according to the above method, context switching is carried out by address conversion. In other words, in a microprocessor, an instruction execution unit and an instruction decoder, which execute programs, and a plurality of registers in which context information is stored are connected via selectors or the like. The microprocessor then specifies the address of a register in which necessary context information is stored, and reads that context information. Therefore, there are numerous interconnects and selectors among the instruction execution unit, the instruction decoder, and the registers in which context information is stored. As a result, the circuit size and power consumption of the microprocessor increase. In addition, numerous connected circuits cause increases in load when writing data to the registers from the instruction execution unit and the instruction decoder.